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Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。
Platform: |
Size: 9734 |
Author: wgy |
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Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: |
Size: 9216 |
Author: wgy |
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Description: ViewPic： display image of yuv420 or yuv422 and size of image are 352*288,352*240,704*576,704*480,720*480.
ViewYUV: display video sequence of yuv 420,and 352x288
记得编译之前需要安装 directx，在vc中指定 directx的include和lib路径-ViewPic: display image of yuv420 or yuv422 and size of image are 352* 288352* 240704* 576704* 480720* 480.ViewYUV: display video sequence of yuv 420, and 352x288 remember before the compiler need to install directx, in vc specified include the directx and lib path
Platform: |
Size: 97280 |
Author: panxi |
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Description: 分析计算高清、标清电视视频序列的PSNR。
给出yuv文件，然后只需代码中给出自己需要是高清的，国标电视视频1920*1080，标清720*576，然后分析各个电视画面帧的PSNR值。-Analysis and Calculation of High Definition, Standard Definition TV video sequences of the PSNR. Give yuv file, then just give the code to their own needs are high-definition, and GB TV Video 1920* 1080, SD 720* 576, and then analyze all the TV screen frame PSNR values.
Platform: |
Size: 7168 |
Author: Freddie |
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Description: 提出一种使用 FPGA 现场可编程门阵列 实现一个 ITU2R BT. 656并行硬件接口传输 4
路 CIF格式视频流的方法。该方法说明了从视频处理器到 FPGA传输 4路 CIF格式视频流的数据结构 ,利用该数据结构 ,一个 ITU2R BT. 656的硬件接口可传输 4路不同的 CIF格式的视频数据流。FP2(GA将 4路视频数据流分离、插值生成 D1 720 ×576像素 格式的数据输出给视频处理器。
Platform: |
Size: 169984 |
Author: cui |
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Description: Convert a fixed resolution(720*576) packed YUV frame to planar format YUV frame.
Platform: |
Size: 1024 |
Author: watersecond |
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Description: SEED-DEC6437平台上的视频回放源代码，分辨率为720*576 -SEED-DEC6437 platform video playback on the source code, a resolution of 720* 576
Platform: |
Size: 1694720 |
Author: 汝建斌 |
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